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ST10F272M bảng dữ liệu(PDF) 100 Page - STMicroelectronics

tên linh kiện ST10F272M
Giải thích chi tiết về linh kiện  16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
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ST10F272M bảng dữ liệu(HTML) 100 Page - STMicroelectronics

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System reset
ST10F272M
100/176
The start-up configurations and some system features are selected on reset sequences as
described in Table 43 and Figure 35.
Table 43 describes the system configuration latched on PORT0 in the six different reset
modes. Figure 35 summarizes the state of bits of PORT0 latched in RP0H, SYSCON,
BUSCON0 registers.
Software Reset (2)
x
0
N
Synch.
Not activated
0
0
0
1
0
x
0
N
Synch.
Not activated
0
0
0
1
0
0
1
Y
Synch.
Not activated
0
0
0
1
0
1
1
Y
Synch.
Activated by internal logic for 1024 TCL
0
0
0
1
0
Watchdog Reset (2)
x
0
N
Synch.
Not activated
0
0
0
1
1
x
0
N
Synch.
Not activated
0
0
0
1
1
0
1
Y
Synch.
Not activated
0
0
0
1
1
1
1
Y
Synch.
Activated by internal logic for 1024 TCL
0
0
0
1
1
1.
It can degenerate into a Long Hardware Reset and consequently differently flagged (see Section 20.3 for details).
2.
When Bidirectional is active (and with RPD = 0), it can be followed by a Short Hardware Reset and consequently differently
flagged (see Section 20.6 for details).
Table 42.
Reset event (continued)
Event
RSTIN
WDTCON flags
Min
Max
Table 43.
PORT0 latched configuration for the different reset events
X: Pin is sampled
-: Pin is not sampled
PORT0
Sample event
Software Reset
-
-
-
XX
XXX
XX
-
-
-
-
-
-
Watchdog Reset
-
-
-
XX
XXX
XX
-
-
-
-
-
-
Synchronous Short Hardware Reset
-
-
-
X
X
X
X
X
X
X
X
X
X
X
X
X
Synchronous Long Hardware Reset
XXX
XX
XXX
XX
XXX
XX
X
Asynchronous Hardware Reset
XXX
XX
XXX
XX
XXX
XX
X
Asynchronous Power-On Reset
XXX
XX
XXX
XX
XXX
XX
X



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