ST10F272M datasheet(85/175 Pages) STMICROELECTRONICS

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ST10F272M

System reset

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behavior when booting from internal or external memory respectively. Figures 23 and 24

report the timing of a typical synchronous Long Reset, again when booting from internal or

external memory.

Synchronous reset and RPD pin

Whenever the RSTIN pin is pulled low (by external hardware or as a consequence of a

Bidirectional reset), the RPD internal weak pull-down is activated. The external capacitance

(if any) on RPD pin is slowly discharged through the internal weak pull-down. If the voltage

level on RPD pin reaches the input low threshold (approximately 2.5V), the reset event

becomes immediately asynchronous. In case of hardware reset (short or long) the situation

goes immediately to the one illustrated in Figure 19. There is no effect if RPD comes again

above the input threshold: the asynchronous reset is completed coherently. To correctly

complete a synchronous reset, the value of the capacitance must be big enough to maintain

a sufficiently high voltage on the RPD pin for the duration of the internal reset sequence.

For a Software or Watchdog reset events, an active synchronous reset is completed

regardless of the RPD status.

It is important to highlight that the signal that makes RPD status transparent under reset is

the internal RSTF (after the noise filter).

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