TDA7410ND datasheet(23/34 Pages) STMICROELECTRONICS

23 / 34 page

TDA7410ND

Functional description of the noiseblanker

23/34

due to the higher noise, which is also rectified. With increasing of the PEAK voltage the

trigger threshold increases, too. This particular gain is programmable in 4 steps (see

Figure 9).

7.3

Automatic threshold control

Besides the noise controlled threshold adjustment there is an additional possibility for

influencing the trigger threshold. It is depending on the stereoblend control. The point where

the MPX signal starts to become noisy is fixed by the RF part. Therefore also the starting

point of the normal noise-controlled trigger adjustment is fixed (Figure 11). In some cases

the behaviour of the noiseblanker can be improved by increasing the threshold even in a

region of higher fieldstrength. Sometimes a wrong triggering occures for the MPX signal

often shows distortion in this range which can be avoided even if using a low threshold.

Because of the overlap of this range and the range of the stereo/mono transition it can be

controlled by stereoblend. This threshold increase is programmable in 3 steps or switched

off with bits D0 and D1 of the fieldstrength control byte.

7.4

Over deviation detector

If the system is tuned to stations with a high deviation the noiseblanker can trigger on the

higher frequencies of the modulation. To avoid this wrong behaviour, which causes noise in

the output signal, the noiseblanker offers a deviation dependent threshold adjustment. By

rectifying the MPX signal a further signal representing the actual deviation is obtained. It is

used to increase the PEAK voltage. Offset and gain of this circuit are programmable in 3

steps with the bits D6 and D7 of the stereodecoder byte (the first step turns off the detector,

see Figure 10).

7.5

Test Mode

During the test mode which can be activated by setting bit D0 of the testing byte and bit D5

of the subaddress byte to ”1” several internal signals are available at the CASSR pin. During

this mode the input resistance of 100kOhm is disconnected from the pin. The internal

signals available are shown in the software specification.

Figure 17.

Application Example

100nF

μF

100nF

VDD

CASS_L

CASS_R

CDR

CDG

CDL

AUX_R

AUX_L

CASS_L

CASS_R

CDR

CDG

CDL

AUX_R

AUX_L

CREF

μF

OUT_LF

OUT_RF

OUT_LR

OUT_RR

MPX

SDA

SCL

MUTE

LEVEL

GND

OUT_LF

OUT_RF

OUT_LR

OUT_RR

MPX

SDA

SCL

MUTE

LEVEL

TDA7410D

100nF

TDA7410ND

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