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Arm Cortex-M3 Datasheet

Datasheet

Overview

The Cortex-M3 processor is specifically developed for high-performance, low-cost platforms

for a broad range of devices including microcontrollers, automotive body systems, industrial

control systems and wireless networking and sensors.

Features

Feature

Description

Architecture

Armv7-M

Bus Interface

3x AMBA AHB-Lite interface (Harvard bus architecture)

AMBA ATB interface for CoreSight debug components

ISA Support

Thumb/Thumb-2 subset

Pipeline

Three-stage

Memory Protection

Optional 8 region MPU with sub regions

and background region

Bit Manipulation

Integrated Bit-field Processing Instructions

and Bus Level Bit Banding

Interrupts

Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts

Interrupt Priority Levels

8 to 256 priority levels

Wake-up Interrupt

Controller

Optional

Enhanced Instructions

Hardware Divide (2-12 Cycles), Single-Cycle (32x32) Multiply,

Saturated Adjustment Support

Sleep Modes

Integrated WFI and WFE Instructions and Sleep On Exit capability

Sleep and Deep Sleep Signals

Optional Retention Mode with Arm Power Management Kit

Debug

Optional JTAG and Serial Wire Debug ports. Up to 8

Breakpoints and 4 Watchpoints

Trace

Optional Instruction (ETM), Data Trace (DWT), and

Instrumentation Trace (ITM)

Figure 1: Block diagram

of the Cortex-M3 processor