7

Feature

Options

Number of interrupts

Specifies number of interrupts (1-240 interrupts)

Levels of interrupt priority

Between 3 and 8 bits of interrupt priority, between 8 and 256 levels

of priority

MPU present

No MPU

MPU present

Bit Banding

Specifies whether bit-banding is present

AHB control

Specifies whether AB-Lite buses maintain control information during

wait stated transfers

Debug level

Specifies the level of debug support (0 to 3)

Trace level

Specifies the level of trace support (0 to 3)

Reset all registers

Specifies whether all synchronous state or only architecturally re-

quired state is reset

JTAG present

Enables or disables the JTAG portion of the debug port

Clock Gate present

Specifies whether architectural clock gates are included

Observation

Enables observation of internal state of the processor

WIC present

Specifies whether a WIC is present

WIC lines

Number of WIC lines (minimum 2)

Processor Configuration Options

The Cortex-M3 processor has configurable options that you can set during the

implementation and integration stages to match your functional requirements.