TUSB1044AI datasheet(38/66 Pages) TI1

38 / 66 page

Table 7-10. I2C Target Address (continued)

TUSB1044A I2C Target Address

UEQ1/A1

PIN LEVEL

UEQ0/A0

PIN LEVEL

BIT 7 (MSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

(W/R)

0/1

7.5.1 Procedure to Write to TUSB1044A I2C Registers:

1. The controller initiates a write operation by generating a start condition (S), followed by the TUSB1044A 7-bit

address and a zero-value W/R bit to indicate a write cycle .

2. The TUSB1044A acknowledges the address cycle.

3. The controller presents the sub-address (I2C register within TUSB1044A4) to be written, consisting of one

byte of data, MSB-first.

4. The TUSB1044A acknowledges the sub-address cycle.

5. The controller presents the first byte of data to be written to the I2C register.

6. The TUSB1044A acknowledges the byte transfer.

7. The controller can continue to present additional bytes of data to be written, where each byte transfer is

complete after an acknowledge from the TUSB1044A.

8. The controller terminates the write operation by generating a stop condition (P).

7.5.2 Procedure to Read the TUSB1044A I2C Registers:

1. The controller initiates a read operation by generating a start condition (S), followed by the TUSB1044A 7-bit

address and a one-value W/R bit to indicate a read cycle

2. The TUSB1044A acknowledges the address cycle.

3. The TUSB1044A transmit the contents of the memory registers MSB-first starting at register 00h or last read

sub-address+1. If a write to the I2C register occurred prior to the read, then the TUSB1044A shall start at the

sub-address specified in the write.

4. The TUSB1044A waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the controller

after each byte transfer; the I2C controller acknowledges reception of each data byte transfer.

5. If an ACK is received, the TUSB1044A transmits the next byte of data.

6. The controller terminates the read operation by generating a stop condition (P).

7.5.3 Procedure to Set a Starting Sub-Address for I2C Reads:

1. The controller initiates a write operation by generating a start condition (S), followed by the TUSB1044A 7-bit

address and a zero-value W/R bit to indicate a write cycle.

2. The TUSB1044A acknowledges the address cycle.

3. The controller presents the sub-address (I2C register within TUSB1044A) to be written, consisting of one

byte of data, MSB-first.

4. The TUSB1044A acknowledges the sub-address cycle.

5. The controller terminates the write operation by generating a stop condition (P).

Note

If no sub-addressing is included for the read procedure, and reads start at register offset 00h and

continue byte by byte through the registers until the I2C controller terminates the read operation. If a

I2C address write occurred prior to the read, then the reads start at the sub-address specified by the

address write.

TUSB1044A

SLLSG07 – MARCH 2025

www.ti.com

Submit Document Feedback

Product Folder Links: TUSB1044A

TUSB1044AI bảng dữ liệu(PDF) 38 Page - Texas Instruments

TUSB1044AI bảng dữ liệu(HTML) 38 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

bảng dữ liệu tải về

Link URL