TUSB1044AI datasheet(35/66 Pages) TI1

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Table 7-6. I2C Configuration Control (continued)

Registers

TUSB1044A

Configuration

VESA® DisplayPort™ Alt

Mode

DFP_D Configuration

USB32_BY

2_EN

DIRSEL1

DIRSEL0

CTLSEL1

CTLSEL0

FLIPSEL

One Port USB 3.2x2 – No

Flip

–

One Port USB 3.2x2 –

With Flip

–

4-Channel Custom Alt

Mode – No Flip

–

4-Channel Custom Alt

Mode – With Flip

–

One Port USB 3.2x2 – No

Flip

–

One Port USB 3.2x2 –

With Flip

–

Table 7-7. I2C AUXP/N to SBU1/2 Mapping

Registers

AUX_SBU_OVR

CTLSEL1

FLIPSEL

Mapping

AUXp -> SBU1

AUXn -> SBU2

AUXp -> SBU2

AUXn -> SBU1

Open

AUXp -> SBU1

AUXn -> SBU2

AUXp -> SBU2

AUXn -> SBU1

Open

7.4.3 DisplayPort Mode

The TUSB1044A supports up to four DisplayPort lanes at data rates up to 10.0Gbps. TUSB1044A can be

enabled for DisplayPort through GPIO control or through I2C register control. When in GPIO mode, DisplayPort

is controlled based on Table 7-3. When not in GPIO mode, enable of DisplayPort functionality is controlled

through I2C registers.

7.4.4 Custom Alternate Mode

The TUSB1044A supports up to two lanes (or four channels) of custom Alternate Mode at data rates up to

10Gbps. The TUSB1044A can be enabled for custom Alternate Mode through GPIO control or through I2C

in GPIO mode, custom Alternate Mode is controlled based on Table 7-3. When not in GPIO mode, enable of

custom Alternate Mode functionality is controlled through I2C registers. In I2C mode, the operation of this mode

requires leaving AUX_SNOOP_DISABLE register 13h bit 7 at 0.

7.4.5 Linear EQ Configuration

TUSB1044A receiver lanes have controls for receiver equalization for upstream and downstream facing ports.

The receiver equalization gain value can be controlled either through I2C registers or through GPIOs. Table 7-8

details the gain value for each available combination when TUSB1044A is in GPIO mode. These same options

are also available per channel and for upstream and downstream facing ports in I2C mode by updating registers

URX[2:1]EQ_SEL, UTX[2:1]EQ_SEL, DRX[2:1]EQ_SEL, and DTX[2:1]EQ_SEL.

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TUSB1044A

SLLSG07 – MARCH 2025

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