KSZ9567R_V01 datasheet(116/233 Pages) MICROCHIP

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KSZ9567R

DS00002329E-page 116

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5.1.6.9

Global PTP Clock Temp Adjustment Duration High Word Register

5.1.6.10

Global PTP Clock Temp Adjustment Duration Low Word Register

5.1.6.11

Global PTP Message Config 1 Register

Address:

0x0510 - 0x0511

Size:

16 bits

Bits

Description

Type

Default

15:0

PTP Temporary Adjustment Duration [31:16]

This sets the duration for the PTP clock temporary rate adjustment, in

number of 25MHz clock cycles.

R/W

0x0000

Address:

0x0512 - 0x0513

Size:

16 bits

Bits

Description

Type

Default

15:0

PTP Temporary Adjustment Duration [15:0]

This sets the duration for the PTP clock temporary rate adjustment, in

number of 25MHz clock cycles.

R/W

0x0000

Address:

0x0514 - 0x0515

Size:

16 bits

Bits

Description

Type

Default

15:8

RESERVED

0x00

Enable IEEE 802.1AS Mode

This bit has no effect unless bit 6 in this register (IEEE 1588 PTP Mode

enable) is also set. When this mode is enabled, it modifies the IEEE 1588

mode behavior. Primarily it causes all PTP messages to be forwarded to the

host port, and the switch will not modify PTP message headers.

1 = enable

0 = disable

R/W

Enable IEEE 1588 PTP Mode

When enabled, the switch detects PTP message types and gives them

special forwarding treatment. The switch can modify the header of PTP

messages and insert timestamps. The internal PTP clock is enabled. The tail

tagging format is altered to accommodate timestamps for PTP messages.

1 = enable

0 = disable

R/W

Enable Detection of IEEE 802.3 Ethernet PTP Messages

1 = enable

0 = disable

R/W

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