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KSZ9567R bảng dữ liệu(PDF) 59 Page - Microchip Technology |
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KSZ9567R bảng dữ liệu(HTML) 59 Page - Microchip Technology |
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59 / 233 page  2022 Microchip Technology Inc. and its subsidiaries DS00002329E-page 59 KSZ9567R The internal registers and tables of the device are accessed using 16-bit addressing and 8-bit data. The access formats are as follows: 4.11.3 MII MANAGEMENT (MIIM) INTERFACE The device supports the IEEE 802.3 MII management interface, also known as the management data input/output (MDIO) interface. This interface allows upper-layer devices to monitor and control the states of the KSZ9567R PHY blocks, but it does not provide access to the switch registers. An external device with MDC/MDIO capability can read the PHY status or configure the PHY settings. Details on the MIIM interface can be found in Clauses 22 and 45 of the IEEE 802.3 Specification. Use of MIIM conflicts with use of the In-Band Management interface. These interfaces cannot be used simultaneously. The MIIM interface consists of the following: • A physical connection that uses a data signal (MDIO) and a clock signal (MDC) for communication between an external controller and the KSZ9567R. Note that the MDIO signal is open-drain. • A specific protocol that operates across the two signal physical connection that allows an external controller to communicate with the internal PHY devices. • Access to a set of standard, vendor-specific and extended (MMD) 16-bit registers. These registers are also directly accessible via the SPI and I2C interface options. FIGURE 4-13: SINGLE BYTE REGISTER WRITE FIGURE 4-14: SINGLE BYTE REGISTER READ FIGURE 4-15: BURST REGISTER WRITE FIGURE 4-16: BURST REGISTER READ |
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