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KSZ9567R bảng dữ liệu(PDF) 184 Page - Microchip Technology |
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KSZ9567R bảng dữ liệu(HTML) 184 Page - Microchip Technology |
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184 / 233 page  KSZ9567R DS00002329E-page 184 2022 Microchip Technology Inc. and its subsidiaries 5.2.11.4 Port PTP Egress Timestamp for Request and Delay High Word Register 5.2.11.5 Port PTP Egress Timestamp for Request and Delay Low Word Register 5.2.11.6 Port PTP Egress Timestamp for Sync High Word Register 5.2.11.7 Port PTP Egress Timestamp for Sync Low Word Register Address: 0xNC08 - 0xNC09 Port N: 1-7 Size: 16 bits Bits Description Type Default 15:0 PTP Port N Egress Timestamp for Pdelay_Req and Delay_Req in Nanoseconds (XDLY_REQ_TS[31:16]) This field contains the Port N egress timestamp high-word value for Pde- lay_Req and Delay_Req frames in nanoseconds. RO 0x0000 Address: 0xNC0A - 0xNC0B Port N: 1-7 Size: 16 bits Bits Description Type Default 15:0 PTP Port N Egress Timestamp for Pdelay_Req and Delay_Req in Nanoseconds (XDLY_REQ_TS[15:0]) This field contains the Port N egress timestamp low-word value for Pde- lay_Req and Delay_Req frames in nanoseconds. RO 0x0000 Address: 0xNC0C - 0xNC0D Port N: 1-7 Size: 16 bits Bits Description Type Default 15:0 PTP Port N Egress Timestamp for Sync in Nanoseconds (SYNC_TS[31:16]) This field contains the Port N egress timestamp high-word value for the Sync frame in nanoseconds. RO 0x0000 Address: 0xNC0E - 0xNC0F Port N: 1-7 Size: 16 bits Bits Description Type Default 15:0 PTP Port N Egress Timestamp for Sync in Nanoseconds (SYNC_TS[15:16]) This field contains the Port N egress timestamp low-word value for the Sync frame in nanoseconds. RO 0x0000 |
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