TMP86CS44UG datasheet(92/172 Pages) TOSHIBA

92 / 172 page

Page 82

9. 16-Bit Timer/Counter2 (TC2)

9.2 Control

TMP86CS44UG

9.2 Control

The timer/counter 2 is controlled by a timer/counter 2 control register (TC2CR) and a 16-bit timer register 2

(TC2DR).

Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care

Note 2: When writing to the Timer Register 2 (TC2DR), always write to the lower side (TC2DRL) and then the upper side

(TC2DRH) in that order. Writing to only the lower side (TC2DRL) or the upper side (TC2DRH) has no effect.

Note 3: The timer register 2 (TC2DR) uses the value previously set in it for coincidence detection until data is written to the upper

side (TC2DRH) after writing data to the lower side (TC2DRL).

Note 4: Set the mode and source clock when the TC2 stops (TC2S = 0).

Note 5: Values to be loaded to the timer register must satisfy the following condition.

TC2DR > 1 (TC2DR15 to TC2DR11 > 1 at warm up)

Note 6: If a read instruction is executed for TC2CR, read data of bit 7, 6 and 1 are unstable.

Note 7: The high-frequency clock (fc) canbe selected only when the time mode at SLOW2 mode is selected.

Note 8: On entering STOP mode, the TC2 start control (TC2S) is cleared to "0" automatically. So, the timer stops. Once the STOP

mode has been released, to start using the timer counter, set TC2S again.

TC2DR

(0025H,

0024H)

9876543210

TC2DRH (0025H)

TC2DRL (0024H)

(Initial value: 1111 1111 1111 1111)

R/W

TC2CR

(0023H)

543

TC2S

TC2CK

TC2M

(Initial value: **00 00*0)

TC2S

TC2 start control

0:Stop and counter clear

1:Start

R/W

TC2CK

TC2 source clock select

Unit : [Hz]

NORMAL1/2, IDLE1/2 mode

Divider

SLOW1/2

mode

SLEEP1/2

mode

R/W

DV7CK = 0

DV7CK = 1

000

fc/223

fs/215

DV21

fs/215

001

fc/213

fs/25

DV11

fs/25

010

fc/28

DV6

–

011

fc/23

DV1

–

100

–

fc (Note7)

–

101

–

110

Reserved

External clock (TC2 pin input)

111

TC2M

TC2 operating mode

select

0:Timer/event counter mode

1:Window mode

R/W

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