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TMP88CS42FG bảng dữ liệu(PDF) 97 Page - Toshiba Semiconductor |
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TMP88CS42FG bảng dữ liệu(HTML) 97 Page - Toshiba Semiconductor |
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97 / 216 page ![]() Page 87 TMP88CS42FG Figure 9-4 External Trigger Mode Timing Chart 9.3.3 Event counter mode In this mode, the timer/counter counts up at the active edge on CTC pin input (rising or falling edge selected with the CTC1CR1<CTC1SE> which is provided for selecting external trigger edge). When the counter value and the set value of the CTC1DRA Register match, an INTCTC1 interrupt is generated and the counter is cleared. After the counter is cleared, it restarts and continues counting up at each edge on CTC pin input. The maximum applied frequency is shown in the table below. Because coincidence detection is made at an edge opposite the selected edge, the external clock signal on CTC pin must always be entered. Figure 9-5 Event Counter Mode Timing Chart 12 0 0 1 n - 1 m 1 3 2 n CTC pin input Internal clock Counter (II) When rising start edge is selected, with counting enabled on both edges ( CTC1SE = 0, CTC1E = 1 ) Timer Register A Count start Count stop Count start INTCTC1 interrupt n Successive Trigger Trigger Trigger 12 0 3 0 2 n 5 0 1 3 4 1 2 CTC pin input Internal clock Counter Timer Register A Count start Count clear Count start INTCTC1 interrupt n One Shot Trigger Trigger Trigger Note) m < n 1 0 2 1 n - 1 n 0 n Timer Register CTC pin input When rising start edge is selected Counter Command start INTCTC1 interrupt |
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