TMP88CS42FG datasheet(92/216 Pages) TOSHIBA

92 / 216 page

Page 82

9. 16-Bit Timer (CTC)

9.2 Control

TMP88CS42FG

9.2 Control

Compare timer/counter 1 is controlled using Compare timer/counter 1 Control Registers (CTC1CR1 and

CTC1CR2), as well as three 16-bit Timer Registers (CTC1DRA, CTC1DRB, and CTC1DRC).

Note: CTC1DRA, CTC1DRB, and CTC1DRC are write-only registers and must not be used with any of the read-modify-write

instructions such as SET, CLR, etc.

Note 1: *: Don’t care

Note 2: The CTC1CR1<CTC1RES> is 0 when read.

Note 3: Use the LDW instruction for write to the CTC1DR H/L Registers. Set a value equal to or greater than 2.

Note 4: Write to CTC1DR H/L A, B, and C Registers as many as set with the CTC1CR2 Register CTC1REG bit.

Note 5: Data are written to CTC1DR H/L Registers in order of CTC1DRA, CTC1DRB, and CTC1DRC.

Compare Timer Registers (CTC1DRH: 00017h, CTC1DRL: 00016h)

CTC1DRA

765

Write only

(Initial value: ******** ********)

CTC1DRAH

CTC1DRAL

CTC1DRB

765

Write only

Initial value: ******** ********

CTC1DRBH

CTC1DRBL

CTC1DRC

765

Write only

Initial value: ******** ********

CTC1DRCH

CTC1DRCL

Compare Timer/Counter 1 Control Registers (CTC1CR2: 00015h, CTC1CR1: 00014h)

CTC1CR1

lower address

5432

R/W

(Initial value: 00000000)

CTC1RES

PPGFF0

CTC1M

CTC1CY

CTC1SE

CTC1E

CTC1SM

CTC1S

CTC1CR2

upper address

5432

R/W

(Initial value: *0000000)

EXTRG-

DIS

CTC1REG

CTC1CK

CTC1FF0

TMP88CS42FG bảng dữ liệu(PDF) 92 Page - Toshiba Semiconductor

TMP88CS42FG bảng dữ liệu(HTML) 92 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL