ADF5612CCCZ datasheet(18/48 Pages) AD

18 / 48 page

Data Sheet

ADF5612

THEORY OF OPERATION

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Rev. 0 | 18 of 48

FRAC2WORD and MOD2WORD are only required if

NFRAC1WORD is not an integer number. If NFRAC1WORD is

an integer, no further calculation is required. In this case,

VAR_MOD_EN is set to 0 to disable FRAC2WORD and

MOD2WORD.

4. Calculate the MOD2WORD as follows:

a. Determine the remainder of the fractional word.

NREMAINDER= NFRAC1WORD

−FRAC1WORD

(13)

NREMAINDER= 25836912.64

−25836912 =0.64

(14)

b. Find the greatest common divisor (GCD) between fFPD and

MOD1WORD × fCHSP.

GCDMOD1WORD×fCHSP, fPFD (15)

GCD225×1, 100MHz= 256 (16)

c. Calculate the initial MOD2WORD calculation as follows:

MOD2WORDINITIAL=

fPFD

GCDMOD1WORD×fCHSP, fPFD

(17)

MOD2WORDINITIAL = 100MHz256 = 390625 (18)

d. Calculate the final MOD2WORD.

To maximize frequency resolution, the final value of

MOD2WORD is calculated by obtaining the highest integer

multiple of the initial MOD2WORD, that is less than or equal

to the MOD2WORDMAX as follows.

MOD2WORD =

INT MOD2WORDMAX

MO2WORDINITIAL

MOD2WORDINITIAL

(19)

Where MOD2WORDMAX is a fixed value of 224 − 1 =

16777215

MOD2WORD =

INT 16777215

390625

×390625

(20)

MOD2WORD =

42×390625 =16406250

(21)

5. Calculate FRAC2WORD as follows:

FRAC2WORD =

INTNREMAINDER×MOD2WORD

(22)

FRAC2WORD =

INT0.64×16406250

(23)

FRAC2WORD = 10500000

(24)

6. Calculate the total N value using the original formula as follows:

N=NINT+FRAC1WORD+FRAC2WORD

MOD2WORD

MOD1WORD

(25)

N=39+25836912+10500000

16406250

33554432

=39.77 (26)

7. Calculate the fRFOUT frequency as follows:

fVCO=fPFD×N

(27)

fRFOUT=2×fVCO

(28)

fRFOUT=2× fPFD×N

(29)

fRFOUT=2× 100MHz×39.77 =

7.954GHz

(30)

CIRCUIT DESCRIPTION

RF Output Divider

The RFOUT_DIV (Register 0x022, Bits[7:5]) is a 3-bit divider used

to divide the frequency seen at the output buffer. The divide

ratio can be set from 1, 2, 4, 8, 16, 32, 64, or 128, offering

a frequency range from 57MHz to 8500MHz. The divider output

power can be set via the DIV_PWR bits (Register 0x022, Bits[2:0]).

The RFOUT_DIV and output divider channels,NDIV_OUT and

PDIV_OUT, can be disabled when not in use via the PD_ODIV

bit (Register 0x028, Bit 1).

The RF output divider channels, NDIV_OUT and PDIV_OUT, can

be either AC- or DC-coupled and terminated with a 100Ω resistor

differentially as shown in Figure 39 and Figure 40. If a single-ended

output is desired, each side of the output must be individually

AC-coupled and terminated with a 50Ω resistor, see Figure 41.

For AC-coupled applications, a series of 0.1μF capacitors must

be connected to the RFOUT, PDIV_OUT, and NDIV_OUT pins as

shown in Figure 42.

Figure 39. Common Clock Interface: Differential Clock with End Termination

(ZO = 50 Ω), AC-Coupled

Figure 40. Common Clock Interface: Differential Clock with End Termination

(ZO = 50 Ω), DC-Coupled

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