| công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
ADF5612CCCZ bảng dữ liệu(PDF) 5 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADF5612CCCZ bảng dữ liệu(HTML) 5 Page - Analog Devices |
|
5 / 48 page ![]() Data Sheet ADF5612 SPECIFICATIONS analog.com Rev. 0 | 5 of 48 Table 1. Specifications (Continued) Parameter Symbol Min Typ Max Unit Test Conditions/Comments VDD3 58 mA Divide by 1 71 mA Divide by 2 77 mA Divide by 4 81 mA Divide by 8 86 mA Divide by 16 88 mA Divide by 32 90 mA Divide by 64 92 mA Divide by 128 VCOVCC 92 mA 5.0V Power-Down PLL4 2.3 µA Power down via the SPI and the PD_RDIV, PD_NDIV, PD_LD, PD_PFDCP, and PD_PFDNCLK bits, see Table 56 and Table 57 VCOVCC5 13 mA Power down via the SPI and the PD_VCO and PD_ADC bits, see Table 56 Divider5 202 μA Power down via the SPI and the PD_ODIV bit, see Table 57 VCO OPEN-LOOP PHASE NOISE RFOUT at 7.3GHz 10kHz Offset −92 dBc/Hz 100kHz Offset −115 dBc/Hz 1MHz Offset −135 dBc/Hz 10MHz Offset −155 dBc/Hz 100MHz Offset −168 dBc/Hz PLL Integer Boundary Spurs −55 dBc LOCKED bit = 1, fREF = fPFD = 100MHz, RDIV = 1, see Figure 29 Phase Frequency Detector (PFD) Spurs −105 dBc LOCKED bit = 1, fREF = 200MHz, fPFD = 100MHz, RDIV = 2, see Figure 30 Reference Spurs −100 dBc LOCKED bit = 1, fREF = fPFD = 100MHz, RDIV = 1, see Figure 31 Normalized Inband Phase Noise Floor Figure of Merit (FOM) LNORM Normalized to 1Hz Floor Integer Mode LNORM_INT −232 dBc/Hz Floor Fractional Mode LNORM_FRAC −229 dBc/Hz Normalized 1/f Phase Noise Floor (Integer and Fractional Mode) L1/f −268 dBc/Hz Integrated RMS Jitter <40 fs Integration bandwidth from 1kHz to 100MHz VCO CHARACTERISTICS Tuning Sensitivity (RFOUT) KVCO 95 to 125 MHz/V 7300MHz to 8500MHz Tune Port Capacitance 155 pF Auto Calibration Time 100 μs Refer to the Total Autocalibration Time section VCO OUTPUT DIVIDER VCO RF Divider Range 1 128 1, 2, 4, 6, 8, 16, 32, 64, or 128 VCO Supply Pushing (VCOVCC)1 0.7 MHz/V PDIV_OUT and NDIV_OUT, divide by 1, VT = 1.65V VCO Supply Pushing (VDD1)5 67 MHz/V PDIV_OUT and NDIV_OUT, divide by 1, VT = 1.65V Divided Reference Clock (DIV_RCLK) VCO Calibration Frequency 50 MHz |
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |