TMP91C025FG datasheet(21/260 Pages) TOSHIBA

21 / 260 page

TMP91C025

2007-02-28

91C025-19

3.3.3

System Clock Controller

The system clock controller generates the system clock signal (fSYS) for the CPU core and

internal I/O. It contains two oscillation circuits and a clock gear circuit for high-frequency

(fc) operation. The register SYSCR1<SYSCK> changes the system clock to either fc or fs,

SYSCR0<XEN> and SYSCR0<XTEN> control enabling and disabling of each oscillator,

and SYSCR1<GEAR0:2> sets the high-frequency clock gear to either 1, 2, 4, 8 or 16 (fc, fc/2,

fc/4, fc/8 or fc/16). These functions can reduce the power consumption of the equipment in

which the device is installed.

The combination of settings <XEN>

= 1, <XTEN> = 0, <SYSCK> = 0 and <GEAR0:2> =

100 will cause the system clock (fSYS) to be set to fc/32 (fc/16 × 1/2) after a reset.

For example, fSYS is set to 1.1 MHz when the 36 MHz oscillator is connected to the X1

and X2 pins.

(1) Switching from NORMAL mode to SLOW mode

When the resonator is connected to the X1 and X2 pins, or to the XT1 and XT2 pins,

the warm-up timer can be used to change the operation frequency after stable

oscillation has been attained.

The warm-up time can be selected using SYSCR2<WUPTM0:1>.

This warm-up timer can be programmed to start and stop as shown in the following

examples 1 and 2.

Table 3.3.1 shows the warm-up time.

Note 1: When using an oscillator (other than a resonator) with stable oscillation, a warm-up

timer is not needed.

Note 2: The warm-up timer is operated by an oscillation clock. Hence, there may be some

variation in warm-up time.

Table 3.3.1 Warm-up Times

Warm-up Time

SYSCR2

<WUPTM1:0>

Change to

NORMAL Mode

Change to

SLOW Mode

01 (2

8/frequency)

7.1 (

μs)

7.8 (ms)

10 (2

14/frequency)

0.455 (ms)

500 (ms)

11 (2

16/frequency)

1.820 (ms)

2000 (ms)

at fOSCH = 36 MHz,

= 32.768 kHz

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