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TMPR3916 bảng dữ liệu(PDF) 198 Page - Toshiba Semiconductor |
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TMPR3916 bảng dữ liệu(HTML) 198 Page - Toshiba Semiconductor |
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198 / 225 page ![]() Chapter 10 Asynchronous Serial Interface (UART) Preliminary 10-23 0 0 START TMPR3916 CCR REGISTER & MUX CONFIGURATION Reset UART: (SIFCR) SWRST = 1 RFRST = 1 FRSTEW = 1 Line Control Register: LSBF = 0 UEPS = 1 UPEN = 1 (Sets MSB first, 8 bit tx, etc) Stop UART Reset (SIFCR) RFRST = 0 FRSTEW = 0 Flow Control Register RCS = 1 RSDR = 0 RTSTL = 0001 enables RTS hardware, storing of received data, sets RTS trigger level to 1 RECEPTION ENDS Check RFDN (number of entries in RX FIFO) in Interrupt Status Register Check Interrupt Register for Frame, Parity, Overrun or Time Out errors Retrieve one entry from RX FIFO ERROR Check RFDN (number of entries in RX FIFO) in the Interrupt Status Register errors BLOCK LENGTH = BLOCK LENGTH - 1 BLOCK LENGTH > 0 ? yes Retrieve the first entry from the RX FIFO STORE THE FIFO ENTRY AS BLOCK LENGTH IN A REGISTER OF TMPR3916F Figure 10.4.2 Example flow for a receive operation. The operations written with the courier font are not to be performed on the UART, but may involve TMPR3916 programming or only software operations. |
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