TMPR3916 datasheet(45/225 Pages) TOSHIBA

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Chapter 1 The TMPR3916

Preliminary

1-8

1.6

Clocks

The TMPR3916 incorporates an eight-times PLL clock generator. Connect a crystal oscillator with 1/8

the frequency of the processor clock (processor clock = TX39 core input clock frequency). To reduce power

dissipation and simplify system design, the TMPR3916 can control the TX39 core operating frequency and

the bus operation reference frequency.

Clock Types:

•

Master clock

Master clock regulates the TMPR3916 operations. The clock is eight times the frequency of the

external crystal oscillator.

•

Processor clock

This clock is used for TMPR3916 processor core operations. It has the same frequency as the master

clock. (When using this clock, set reduced frequency indicator RF[1:0] of the core configuration register

to 00. The processor clock will not operate if RF is set to any other value.)

•

System clock

The system clock regulates the TMPR3916 bus operations. It is generated from the processor clock

and is of the same frequency and phase. This clock is output to pin SYSCLK.

Setting the CLKEN pin to low stops all clocks of the device. The SYSCLK pin is set to high in this state

and power-consumption is reduced to a minimum. The processor can resume its function immediately after

the CLKEN pin has been asserted. For further information see chapter “Electrical Characteristics”.

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