TMPR3916 datasheet(197/225 Pages) TOSHIBA

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Chapter 10 Asynchronous Serial Interface (UART)

Preliminary

10-22

START

TMPR3916 CCR REGISTER &

MUX CONFIGURATION

Reset UART: (SIFCR)

SWRST = 1

TFRST = 1

FRSTEW = 1

Line Control Register:

LSBF = 0

UEPS = 1

UPEN = 1

(Sets MSB first, 8 bit tx, etc)

Interrupt Control Register:

CTSAC = 01

sets CTS active status to rising

edge

Stop UART Reset (SIFCR)

TFRST = 0

FRSTEW = 0

Flow Control Register

TRS = 1

RSDR = 0

TSDR = 0

enables CTS hardware, storing of

received data.

BLOCK LENGTH >

0 ?

Check TXALS in

SISCISR (TX FIFO

empty)

TRANSMISSION

ENDS

STORE 2 ENTRIES

IN TX FIFO

SET BLOCK LENGTH

BLOCK LENGTH >

1 ?

STORE 1 ENTRY IN

TX FIFO

STORE BLOCK LENGTH IN TX

FIFO

BLOCK LENGTH =

BLOCK LENGTH - 2

BLOCK

LENGTH =

BLOCK LENGTH - 1

Figure 10.4.1 Example flow for a transmit operation. The operations written with the courier font are not

to be performed on the UART, but may involve TMPR3916 programming or only software

operations.

10.4.2

Receiver programming

In case of a reception operation, the flow of a simple driver could be like the one depicted in Figure

10.4.2. Here the parameters used to program the UART are:

•

8 bit data length

•

1 stop bit

•

even parity

•

MSB first

•

RTS hardware flow control

•

Software operates in polling mode

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