TMPR3916 datasheet(182/225 Pages) TOSHIBA

182 / 225 page

Chapter 10 Asynchronous Serial Interface (UART)

Preliminary

10-7

10.1.8

Parity Control

During transmission, parity information is generated when the data is written to the transmitter shift

•

in bit 7 of the transmitter shift register for 7-bit data length or

•

in TWUB of the line control register for 8-bit data length.

During reception, the parity check is executed when the data is written from receiver shift register to

the receiver buffer. A parity error occurs when a difference between received and calculated parity bit is

found. The check information is stored

•

in bit 7 of the read buffer for 7-bit data length or

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in RWUB of the line control register for 8-bit data length.

10.1.9

Interrupts

The UART can send three interrupt signals to the Interrupt Controller of the TMPR3916:

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Transmit Interrupt

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Receive Interrupt

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Exception Interrupt

A brief explanation of the meaning of each of these interrupts now follows, for further details refer to

the Registers section of the document. It is possible to mask the interrupts by programming the SIDICR

Transmit Interrupt

A Transmit Interrupt may occur when:

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There is free space in the TX FIFO, hence new data may be written in the FIFO.

Receive Interrupt

A Receive Interrupt may occur when:

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There is valid data in the RX FIFO, which has not been retrieved yet.

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There is a Time Out on the Receiver and the Time Out is mapped on the RX interrupt

(programming RIR bit of Interrupt Control Register)

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There is an error (parity, frame or overrun) detected in the RX FIFO.

Exception Interrupt

A Status Interrupt may occur when:

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There is a BREAK in the UART transfer (see section “10.1.11 Breaks”).

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All data in transmit FIFO has been sent.

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There is free space in TX FIFO.

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A CTS active has been detected by the transmitter.

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There is an Overrun Error.

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There is a Frame error.

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There is a Parity error.

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