TMPR3916 datasheet(145/225 Pages) TOSHIBA

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Chapter 7 CAN Module (TXCAN)

Preliminary

7-24

Mailbox Interrupt Flag Registers (MBTIF/MBRIF)

Bit

Name



MBTIF

Bit

Name

MBRIF

There are two interrupt flag registers. One for receive mailboxes and one for transmit mailboxes. If a

mailbox is configured as receive, the corresponding bits in the transmit interrupt flag register MBTIF

will always be read as “0”. In MBTIF, bit 15 is not implemented, because mailbox 15 is the receive-

only mailbox. Bit 15 of MBTIF will always be read as “0”. If a mailbox is configured as transmit, the

corresponding bits in MBRIF will always be read as “0”.

If a message has been received for mailbox “n” and the mask bit is set to “1” the corresponding

interrupt flag “n” of MBRIF will be set to “1” and the interrupt line IRQ0 goes active high (“1”).

If a message has been transmitted from mailbox “n” and the mask bit is set to “1” the corresponding

interrupt flag “n” of MBTIF will be set to “1” and the interrupt line IRQ1 goes active high (“1”).

If the mask bit in MBIM is set to “0”, the interrupt flag in MBRIF or MBTIF will not be set and no

interrupt will be generated. The information about a successful transmission or reception could be read

from the TA or RMP register respectively.

The interrupt output lines IRQ0 and IRQ1 will stay at “1” as long as one of the interrupt flags in

MBRIF or MBTIF are “1” respectively and the corresponding bits in MBIM are set to “1”.

The interrupt flags in MBTIF will be cleared by writing a “1” from the MCU to MBTIF and the

interrupt flags in MBRIF will be cleared by writing a “1” to MBRIF. Writing a “0” has no effect. The

corresponding status flags in TA or RMP have to be cleared separately.

After power-up, all interrupt flags are cleared.

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