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TMPR3916 bảng dữ liệu(PDF) 117 Page - Toshiba Semiconductor |
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TMPR3916 bảng dữ liệu(HTML) 117 Page - Toshiba Semiconductor |
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117 / 225 page  Chapter 6 Direct Memory Access Controller (DMAC) Preliminary 6-4 6.1.3 Potential Problems One of the following reasons can be responsible for an error: • The software has made invalid settings in the Operation Definition Register (ODR) or in the Channel Control Register (CCR). • The software has defined an address in the Source or Destination Address Register (SAR or DAR) that does not exist. The access to this address has caused a bus error. • Either the byte count, the source address or the destination address is not correctly aligned. The DMA Controller sends an interrupt, when an error occurs. These steps need to be executed in case of an error: 1. Read the contents of the Channel Error Register (CER) to get the cause of the error. 2. For details see the register description. 3. Write 0x80 into the Channel Control Register (CCR). 4. Write 0x00 into the Channel Status Register (CSR). 5. Start the whole DMA programming procedure from the first point. |
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