IIS2DULPX datasheet(8/106 Pages) STMICROELECTRONICS

tên linh kiện	IIS2DULPX

Giải thích chi tiết về linh kiện	Intelligent ultralow-power accelerometer for industrial applications

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2.4

Communication interface characteristics

2.4.1

SPI - serial peripheral interface

Subject to general operating conditions for VDD and Top.

Table 6. SPI target timing values

Symbol

Parameter

Value(1)

Unit

Min

Typ

Max

fc(SPC)

SPI clock frequency

MHz

tc(SPC)

SPI clock period

100

thigh(SPC)

SPI clock high

tlow(SPC)

SPI clock low

tsu(CS)

CS setup time (mode 3)

CS setup time (mode 0)

th(CS)

CS hold time (mode 3)

CS hold time (mode 0)

tsu(SI)

SDI input setup time

th(SI)

SDI input hold time

tv(SO)

SDO valid output time

tdis(SO)

SDO output disable time

Cload

Bus capacitance

100

1. Values are evaluated at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not

tested in production

Figure 3. SPI target timing in mode 0

SPC

SDI

SDO

MSB OUT

MSB IN

LSB OUT

LSB IN

tlow(SPC)

v(SO)

tc(SPC)

thigh(SPC)

tsu(CS)

th(SI)

tsu(SI)

dis(SO)

h(CS)

IIS2DULPX

Mechanical and electrical specifications

DS14580 - Rev 1

page 8/106

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