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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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STM32H562VG bảng dữ liệu(PDF) 61 Page - STMicroelectronics |
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STM32H562VG bảng dữ liệu(HTML) 61 Page - STMicroelectronics |
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61 / 270 page  DS14258 Rev 5 61/270 STM32H562xx and STM32H563xx Functional overview 62 • Double-buffered bulk/isochronous endpoint support • USB suspend/resume operations • Frame-locked clock pulse generation • USB 2.0 Link power management support • Battery charging specification revision 1.2 support in device 3.43 USB Type-C/USB Power Delivery controller (UCPD) The devices embed one controller (UCPD) compliant with USB Type-C Cable and Connector Specification release 2.0 and USB Power Delivery Rev. 3.0 specifications. The controller uses specific I/Os supporting the USB Type-C and USB power delivery requirements, featuring: • USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors • “Dead battery” support • USB power delivery message transmission and reception • FRS (fast role swap) support The digital controller handles: • USB Type-C level detection with debounce, generating interrupts • FRS detection, generating an interrupt • Byte-level interface for USB power delivery payload, generating interrupts (DMA compatible) • USB power delivery timing dividers (including a clock pre-scaler) • CRC generation/checking • 4b5b encode/decode • Ordered sets (with a programmable ordered set mask at receive) • Frequency recovery in receiver during preamble The interface offers low-power operation compatible with Stop mode, maintaining the capacity to detect incoming USB power delivery messages and FRS signaling. 3.44 Ethernet MAC interface with dedicated DMA controller (ETH) The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for Ethernet LAN communications through an industry-standard medium-independent interface (MII) or a reduced medium-independent interface (RMII). The microcontroller requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller. The devices include the following features: • Support of 10 and 100 Mbit/s rates • Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors • Tagged MAC frame support (VLAN support) • Half-duplex (CSMA/CD) and full-duplex operation |
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