29PL256N datasheet(21/74 Pages) SPANSION

21 / 74 page

June 6, 2007 S29PL-N_00_A5

S29PL-N MirrorBit

™ Flash Family

Da ta

Shee t

(Prelim i nar y )

7.1.1

Dual Chip Enable Device Description and Operation (PL129N Only)

The dual CE# product (PL129N) offers a reduced number of address pins to accommodate processors with a

limited addressable range. This product operates as two separate devices in a single package and requires

the processor to address half of the memory space with one chip enable and the remaining memory space

with a second chip enable. For more details on the addressing features of the Dual CE# device refer to

Table 6.3 on page 19 for the PL129N Sector and Memory Address Map.

Dual chip enable products must be setup appropriately for each operation. To place the device into the active

state either CE1# or CE2# must be set to VIL. To place the device in standby mode, both CE1# and CE2#

must be set to VIH. Table 7.2 describes the required state of each control pin for any particular operation.

Legend

L = Logic Low = VIL

H = Logic High = VIH

VID = 11.5–12.5 V

VHH = 8.5– 9.5V

X = Don’t Care

SA = Sector Address

AIN = Address In

DIN = Data In

DOUT = Data Out

Notes

1. The sector and sector unprotect functions may also be implemented by programming equipment.

2. WP#/ACC must be high when writing to the upper two and lower two sectors.

7.2

Asynchronous Read

The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory content occurs during the power transition. No command is

necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses

on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for

read access until the command register contents are altered.

7.2.1

Non-Page Random Read

Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable

access time (tCE) is the delay from the stable addresses and stable CE# to valid data at the output inputs. The

output enable access time is the delay from the falling edge of the OE# to valid data at the output (assuming

the addresses have been stable for at least tACC –tOE time).

Table 7.2 Dual Chip Enable Device Operation

Operation

CE1#

CE2#

OE#

WE#

RESET#

WP#/ACC

Addresses

(A21–A0)

DQ15–DQ0

Read

AIN

DOUT

Write

(Note 2)

AIN

DIN

Standby

High-Z

Output Disable

High-Z

Reset

High-Z

Temporary Sector Unprotect

(High Voltage)

XXX

VID

XAIN

DIN

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