29PL256N datasheet(49/74 Pages) SPANSION

49 / 74 page

June 6, 2007 S29PL-N_00_A5

S29PL-N MirrorBit

™ Flash Family

Da ta

Shee t

(Prelim i nar y )

8.7

Hardware Data Protection Methods

The device offers data protection at the sector level via hardware control:

When WP#/ACC is at VIL, the four outermost sectors are locked (device specific).

There are additional methods by which intended or accidental erasure of any sectors can be prevented via

hardware means. The following subsections describes these methods:

8.7.1

WP# Method

The Write Protect feature provides a hardware method of protecting the four outermost sectors. This function

is provided by the WP#/ACC pin and overrides the previously discussed Sector Protection/Unprotection

method.

If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the

outermost boot sectors. The outermost boot sectors are the sectors containing both the lower and upper set

of sectors in a dual-boot-configured device.

If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the boot sectors were last set to

be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether

they were last protected or unprotected.

Note that the WP#/ACC pin must not be left floating or unconnected as inconsistent behavior of the device

may result.

The WP#/ACC pin must be held stable during a command sequence execution

8.7.2

Low VCC Write Inhibit

When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC

power-up and power-down.

The command register and all internal program/erase circuits are disabled, and the device resets to reading

array data. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the

proper signals to the control inputs to prevent unintentional writes when VCC is greater than VLKO.

8.7.3

Write Pulse Glitch Protection

Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.

8.7.4

Power-Up Write Inhibit

If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept commands on the

rising edge of WE#. The internal state machine is automatically reset to the read mode on powerup.

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