Operating modes

M41T256Y

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2.5

Sleep mode

In order to minimize the battery current draw while in storage, the M41T256Y provides the

user with a battery “sleep mode,” which disconnects the RAM memory array from the

external Lithium battery normally used to provide non-volatile operation in the absence of

not needed.

Note:

The sleep mode will remove power from the RAM array only and not affect the data retention

of the TIMEKEEPER Registers (7FF0h through 7FFFh - this includes the Calibration

Register).

The sleep mode (SLP) Bit located in register 7FF8h (D6), must be set to a '1' by the user

disconnect the RAM array from power until the next power-down cycle. This protects the

from the battery, resulting in both a lower battery current, and a loss of RAM data.

Note:

Upon initial battery attach or initial power application without the battery, the state of the SLP

Bit will be undetermined. Therefore, the SLP Bit should be initialized to '0' by the user.

Additional current reduction can be achieved by setting the STOP (ST) Bit in register 7FF9h

(D7), turning off the clock oscillator. This combination will result in the longest possible

battery life, but also loss of time and data. When the device is again powered-up, the user

should first read the SLP Bit to determine if the device is currently in sleep mode, then reset

the bit to '0' in order to disable the sleep mode (this will NOT be automatically taken care of

during the power-up).

Note:

See AN1570, “M41T256Y Sleep Mode Function” for more information on sleep mode and

battery lifetimes.