M41T256Y

Operating modes

15/30

2.3

Write mode

In this mode the master transmitter transmits to the M41T256Y slave receiver. Bus protocol

is shown in Figure 10 on page 15. Following the START condition and slave address, a logic

'0' (R/W=0) is placed on the bus and indicates to the addressed device that byte addresses

A(0) and A(1) will follow and is to be written to the on-chip address pointer (MSB of address

byte A(0) is a “Don’t care”).

The data byte to be written to the memory is strobed in next and the internal address pointer

is incremented to the next memory location within the RAM on the reception of an

acknowledge bit. The M41T256Y slave receiver will send an acknowledge bit to the master

transmitter after it has received the slave address (see Figure 7 on page 13) and again after

it has received each address byte.

Figure 10.

Write mode sequence

2.4

Data retention mode

WRITE cycles. Should the supply voltage decay, the M41T256Y will automatically deselect,

accomplished by internally inhibiting access to the clock registers. At this time, the reset pin

attached battery supply.

Figure 14 on page 25).

For a further more detailed review of lifetime calculations, please see Application Note

AN1012.

AI04761

BUS ACTIVITY:

S

P

SDA LINE

BUS ACTIVITY:

MASTER

DATA n

DATA n+X

BYTE

ADDRESS (0)

SLAVE

ADDRESS

BYTE

ADDRESS (1)