WM8580 datasheet(7/97 Pages) WOLFSON

7 / 97 page

Production Data

WM8580

PD Rev 4.3 August 2007

Notes for MFP1:

ADC_CLKSEL selected in REG 8, default is ADC_MCLK.

PAIFTXMS_CLKSEL selects PLLACLK if PAIF sources SPDIF Rx, otherwise PAIFTXMS_CLKSEL selects ADC_CLK

(register 8)

MFP2 usage can be described as follows:

(ADC_CLKSEL ≠ ADCMCLK)

(controlled by reg 8)

AND

(TX_CLKSEL ≠ ADCMCLK)

(controlled by reg 8)

AND

(SAIFMS_CLKSEL ≠ ADCMCLK) THEN

(controlled by reg 8)

MFP2 = GPO2;

ELSE

MFP2 = ADCMCLK;

PIN FUNCTION

TYPE

DESCRIPTION

PAIFTX_BCLK

Digital Input/Output

Primary Audio Interface Transmitter (PAIFTX) Bit Clock

ADCMCLK

Digital Input

Master ADC clock; 256fs, 384fs, 512fs ,786fs, 1024fs or 1152fs

SAIF_DIN

Digital Input

Secondary Audio Interface (SAIF) Receiver data input

SAIF_DOUT

Digital Output

Secondary Audio Interface (SAIF) Transmitter data output

SAIF_BCLK

Digital Input/Output

Secondary Audio Interface (SAIF) Bit Clock

SAIF_LRCLK

Digital Input/Output

Secondary Audio Interface (SAIF) Left/Right Word Clock

SPDIFIN2/3/4

Digital Input

S/PDIF Receiver Input

GPO1 – GPO10

Digital Output

General Purpose Output

DR1/2/3/4

Digital Input

Internal Digital Routing Configuration in Hardware Mode

ALLPD

Digital Input

Chip Powerdown in Hardware Mode

Digital Output

Recovered channel-bit for current S/PDIF sub-frame

SFRM_CLK

Digital Output

Indicates current S/PDIF sub-frame:

1 = Sub-frame A

0 = Sub-frame B

192BLK

Digital Output

Indicates start of S/PDIF 192-frame block. High for duration of frame 0.

Table 2 Multi-Function Pin Description

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