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ST1S10 bảng dữ liệu(PDF) 14 Page - STMicroelectronics |
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ST1S10 bảng dữ liệu(HTML) 14 Page - STMicroelectronics |
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14 / 26 page ![]() Layout considerations ST1S10 14/26 6 Layout considerations Layout is an important step in design for all switching power supplies. High-speed operation (900 kHz) of the ST1S10 device demands careful attention to PCB layout. Care must be taken in board layout to get device performance, otherwise the regulator could show poor line and load regulation, stability issues as well as EMI problems. It is critical to provide a low inductance, impedance ground path. Therefore, use wide and short traces for the main current paths. The input capacitor must be placed as close as possible to the IC pins as well as the inductor and output capacitor. Use a common ground node for power ground and a different one for control ground (AGND) to minimize the effects of ground noise. Connect these ground nodes together underneath the device and make sure that small signal components returning to the AGND pin and do not share the high current path of CIN and COUT. The feedback voltage sense line (VFB) should be connected right to the output capacitor and routed away from noisy components and traces (e.g., SW line). Its trace should be minimized and shielded by a guard-ring connected to the ground. Figure 6. PCB layout suggestion V FB guard-ring Input capacitor C1 must be placed as close as possible to the IC pins as well as the inductor L1 and output capacitor C2 Vias from thermal pad to bottom layer 47mm CN1=Input power supply CN2=Enable/Disable CN3=Input sync. CN4=V OUT V FB guard-ring Input capacitor C1 must be placed as close as possible to the IC pins as well as the inductor L1 and output capacitor C2 Vias from thermal pad to bottom layer 47mm CN1=Input power supply CN2=Enable/Disable CN3=Input sync. CN4=V OUT |
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