Data Sheet

AD3530/AD3530R

SPECIFICATIONS

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Rev. 0 | 6 of 45

TIMING CHARACTERISTICS

All input signals are specified with rise time (tR) = fall time (tF) = 1ns/V (10% to 90% of VDD) and timed from a voltage level of (VINL + VINH)/2.

VDD = 2.7V to 5.5V, 1.08V ≤ IOVDD ≤ 1.98V, and VREF = 2.5V. All specifications are TJ = −40°C to +125°C, unless otherwise noted.

Table 4. SPI Interface Timing Specifications

Parameter

Description

Min

Typ

Max

Unit

t1

SCLK cycle time

20

ns

801

t2

SCLK high time

t1/2

ns

t3

SCLK low time

t1/2

ns

t4

SCLK rising edge to CSB falling edge

10

ns

t5

CSB falling edge to SCLK rising edge setup time

7

ns

t6

SCLK rising edge to CSB rising edge

4

ns

t7

CSB rising edge to SCLK rising edge

6

ns

t8

Data hold time

2

ns

t9

Data setup time

5

ns

t10

CSB high time (single, combined, or all channel update)

10

ns

t11

SCLK falling edge to SDO data available

9

ns

t12

SCLK falling edge to SDO data remains valid

10

ns

t13

CSB rising edge to SDO disabled

9

ns

t14

SCLK falling edge to SDO enabled

10

ns

t15

Last SCLK rising edge to VOUT transition start

3

μs

t16

RESETB pulse width

2.5

μs

t17

RESETB falling edge to VOUT transition

3

μs

t18

RESETB rising edge to SPI transaction begin

150

ns

1 Only applicable for stream mode functionality.

Figure 2. Serial Read and Write Operation