DSP56303 datasheet(167/292 Pages) FREESCALE

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GPIO Signals and Registers

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

7-35

signal line. If a port signal PC[i] or PD[i] is configured as an output (GPO), a value written to the

corresponding PDRC[i] pr PDRD[i] bit is reflected as a value on the output signal line. Either a

hardware RESET signal or a software RESET instruction clears all PDRC and PDRD bits.

PDRx5

PDRx4

PDRx3

PDRx2

PDRx1

PDRx0

Note:

For bits 5–0, the value represents the level that is written to or read from the associated signal line if it is

enabled as a GPIO signal by the respective port control register (PCRC or PCRD) bits. For ESSI0, the GPIO

signals are PC[5–0]. For ESSI1, the GPIO signals are PD[5–0]. The corresponding data bits for Port C

GPIOs are PDRC[5–0]. The corresponding data bits for Port D GPIOs are PDRD[5–0].

= Reserved. Read as zero. Write with zero for future compatibility.

Figure 7-20. Port Data Registers (PDRC X:$FFFFBD) (PDRD X: $FFFFAD)

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