DSP56303 datasheet(59/292 Pages) FREESCALE

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DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

4-1

Core Configuration

This chapter presents DSP56300 core configuration details specific to the DSP56303, including:

Operating modes

Bootstrap program

Central Processor registers

— Status register (SR)

— Operating mode register (OMR)

Interrupt Priority Registers (IPRC and IPRP)

PLL control (PCTL) register

Bus Interface Unit registers

— Bus Control Register (BCR)

— DRAM Control Register (DCR)

— Address Attribute Registers (AAR[3–0])

DMA Control Registers 5–0 (DCR[5–0])

Device identification register (IDR)

JTAG identification register

JTAG boundary scan register (BSR)

For information on specific registers or modules in the DSP56300 core, refer to the DSP56300

Family Manual.

4.1 Operating Modes

The DSP56303 begins operation by leaving the Reset state and going into one of eight operating

modes. As the DSP56303 exits the Reset state, it loads the values of MODA, MODB, MODC, and

MODD

into bits MA, MB, MC, and MD of the OMR. These bit settings determine the DSP

operating mode, which in turn determines the bootstrap program option the DSP uses to start up.

Software can also set the OMR[MA–MD] bits directly. A jump directly to the bootstrap program

entry point ($FF0000) after the OMR bits are set causes the DSP56303 to execute the specified

bootstrap program option (except modes $0 and $8). Table 4-1 shows the DSP56303 bootstrap

operation modes, the corresponding settings of the external operational mode signal lines (the

OMR[MA–MD] bits), and the reset vector address to which the DSP56303 jumps once it leaves

the Reset state.

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