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ELANSC310 bảng dữ liệu(PDF) 114 Page - Advanced Micro Devices

tên linh kiện ELANSC310
Giải thích chi tiết về linh kiện  Single-Chip, 32-Bit, PC/AT Microcontroller
PDF  119 Pages
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nhà sản xuất  AMD [Advanced Micro Devices]
Trang chủ  http://www.amd.com
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ELANSC310 bảng dữ liệu(HTML) 114 Page - Advanced Micro Devices

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114
Élan™SC310 Microcontroller Data Sheet
PREL IMINARY
These timings are based on default settings and required initial programming. These timings may be modified via the MMS
Memory Wait State1 Register, Index 62h, and the Command Delay Register, Index 60h. (See the ÉlanTMSC310 Microcontroller
Programmer’s Reference Manual,
order #20665.)
1. These timing apply to the B4 version of the ÉlanSC310 microcontroller only. The timings for the B3 version are
t5b = 260 ns, t6b = 0 ns, t12b = -2 ns, and t14 = -4 ns.
Table 59.
ISA I/O 16-Bit Read/Write Cycle (See Figure 48)
Symbol
Parameter Description
Notes
Preliminary
Units
Min
Max
t1a
SA stable to IOW active
200
ns
t1b
SA stable to IOR active
150
ns
t2
SA stable to IOCS16 active
95
ns
t3a
IOW active to IOCHRDY inactive
30
ns
t3b
IOR active to IOCHRDY inactive
80
ns
t4a
IOW hold from IOCHRDY active
110
ns
t4b
IOR hold from IOCHRDY active
160
ns
t5a
IOW pulse width
160
ns
t5b
IOR pulse width
1
225
ns
t6a
SA hold from IOW inactive
50
ns
t6b
SA hold from IOR inactive
1
50
ns
t7
RDDATA setup to command inactive
40
ns
t8
RDDATA hold from command inactive
0
ns
t9
WRDATA setup to command inactive
250
ns
t10
WRDATA hold from command inactive
50
ns
t11
DBUFOE active from command
5
ns
t12a
DBUFOE hold from command Write
50
ns
t12b
DBUFOE hold from command Read
1
50
ns
t13
ENDRIH, ENDIRL setup to IOR
100
ns
t14
ENDIRH, ENDIRL hold from IOR
150
ns
t15
BALE pulse width
50
ns



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