RTL2832U datasheet(13/53 Pages) REALTEK

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Realtek

RTL2832U

Datasheet

DVB-T COFDM Demodulator + USB 2.0

Track ID: JATR-2265-11

Rev. 1.4

7. Functional Description

The block diagram of the RTL2832U DVB-T demodulator is shown in Figure 1, page 3. The RTL2832U

accepts IF or Zero IF input signals with the analog signal sampled by the internal ADC. The sampled data

stream is then processed by OFDM demodulation. After decoding by an on-chip FEC (Viterbi and

Reed-Solomon decoder) the USB 2.0 interface outputs packets with transport stream data.

A detailed description of each block is given in this section.

7.1. Analog-to-Digital Conversion (ADC)

The internal A/D converter can accept tuner output with various bandwidths (6, 7, 8MHz), different IF

frequencies (4.57M or 36.167M,), Zero IF (I & Q channel) input and can perform spectrum reversion.

Using a sampling clock generated by the internal PLL with a 28.8MHz clock source, the RTL2832U

demodulates the received TV signal.

7.2. Automatic Gain Control (AGC)

The AGC circuit is used to adjust received signal strength to a moderate level for the ADC. This module

supports two output paths, and both are sigma-delta modulated signals. The output signals need additional

RC LPFs (Low-Pass Filters) before feeding to IF and RF VGA in the tuner The delayed AGC algorithm

is described in section 8.1 Automatic Gain Control (AGC), page 11.

7.3. Digital Down Conversion

The RTL2832U uses IF or Zero-IF sampling to process received signals. The Digital Down Conversion

(DDC) circuit converts the sampled IF signal to a complex base-band signal for further processing. The

down conversion frequency and low-pass filter can be programmed according to different IF frequency,

sampling rates, and signal bandwidth.

RTL2832U bảng dữ liệu(PDF) 13 Page - Realtek Semiconductor Corp.