MPC8280 datasheet(191/1386 Pages) FREESCALE

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System Interface Unit (SIU)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

4-19

The SIPRR register bits are described in Table 4-5.

4.3.1.3

CPM Interrupt Priority Registers (SCPRR_H and SCPRR_L)

The CPM high interrupt priority register (SCPRR_H), shown in Figure 4-12, define priorities between the

FCCs and MCCs.

Table 4-5. SIPRR Field Descriptions

Bits

Name

Description

0–2

XS1P–XSIU1

Priority order. Defines which PIT/TMCNT/PCI/IRQs asserts its request in the XSIU1 priority

position. The user should not program the same PIT/TMCNT/PCI/IRQs to more than one

priority position (1–8). These bits can be changed dynamically.

000 TMCNT asserts its request in the XSIU1 position.

001 PIT asserts its request in the XSIU1 position.

010 PCI asserts its request in the XSIU1 position.

011 IRQ1 asserts its request in the XSIU1 position.

100 IRQ2 asserts its request in the XSIU1 position.

101 IRQ3 asserts its request in the XSIU1 position.

110 IRQ4 asserts its request in the XSIU1 position.

111 IRQ5 asserts its request in the XSIU1 position.

3–11,

16–27

XS2P– XS8P

Same as XS1P, but for XSIU2–XSIU8.

12–15,

28–31

—

Reserved, should be cleared.

Field

XC1P

XC2P

XC3P

XC4P

—

Reset

000

001

010

011

0000

R/W

Addr

0x10C14

Field

XC5P

XC6P

XC7P

XC8P

—

Reset

100

101

110

111

0000

R/W

Addr

0x10C16

Figure 4-12. CPM High Interrupt Priority Register (SCPRR_H)

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