MPC8280 datasheet(1276/1386 Pages) FREESCALE

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FCC HDLC Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

37-14

Freescale Semiconductor

37.9

HDLC Event Register (FCCE)/Mask Register (FCCM)

The FCCE is used as the HDLC event register when the FCC operates as an HDLC controller. The FCCE

reports events recognized by the HDLC channel and generates interrupts. On recognition of an event, the

HDLC controller sets the corresponding FCCE bit. FCCE bits are cleared by writing ones; writing zeros

does not affect bit values. All unmasked bits must be cleared before the CP clears the internal interrupt

request.

Interrupts generated by the FCCE can be masked in the HDLC mask register (FCCM), which has the same

bit format as FCCE. If an FCCM bit = 1, the corresponding interrupt in the event register is enabled. If the

bit is 0, the interrupt is masked.

Figure 37-7 represents the FCC/FCCM.

Field

—

GRA

—

TXE

RXF

BSY

TXB

RXB

Reset

0000_0000_0000_0000

R/W

Addr

0x11310 (FCCE1), 0x11330 (FCCE2), 0x11350 (FCCE3)/

0x11314 (FCCM1), 0x11334 (FCCM2), 0x11354 (FCCM3)

Field

—

FLG

IDL

—

Reset

0000_0000_0000_0000

R/W

Addr

0x11312 (FCCE1), 0x11332 (FCCE2), 0x11352 (FCCE3)/

0x11316 (FCCM1), 0x11336 (FCCM2), 0x11356 (FCCM3)

Figure 37-7. HDLC Event Register (FCCE)/Mask Register (FCCM)

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