MPC8280 datasheet(1271/1386 Pages) FREESCALE

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FCC HDLC Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

37-9

37.7

HDLC Receive Buffer Descriptor (RxBD)

The HDLC controller uses the RxBD to report on data received for each buffer. Figure 37-4 shows an

example of the RxBD process.

NBL

Nibble mode enable

0 Nibble mode disabled (1 bit of data per clock). Note that at the end of the frame (after the closing

flag), RTS negates immediately after the active edge of TCLK.

1 Nibble mode enabled (4 bits of data per clock). The negation of the RTS output signal is not

synchronized to the serial clock. The RTS is negated after the last nibble of the data and always

before the next edge of the serial clock. Note that at the end of the frame (after the closing flag),

RTS negates a maximum of 5 CPM clocks after the active edge of TCLK.

17–23

—

Reserved, should be cleared.

24-25

CRC

CRC selection

00 16-bit CCITT-CRC (HDLC). X16 + X12 + X5 + 1

01 Reserved

10 32-bit CCITT-CRC (Ethernet and HDLC). X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +

X8 + X7 + X5 + X4 + X2 + X1 +1

11 Reserved

26–31

—

Reserved, should be cleared.

1 When operating an FCC in HDLC nibble mode with the multiframe per FIFO bit off (FPSMR[MFF] = 0), the CPM might

lose synchronization with the FCC HDLC controller. As a result the HDLC controller will become stuck and stop

transmission. Therefore in HDLC nibble mode, FPSMR[MFF] must be set or the FCC must alternatively operate in

HDLC bit mode.

Table 37-6. FPSMR Field Descriptions (continued)1

Bits

Name

Description

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