MPC8280 datasheet(1246/1386 Pages) FREESCALE

1246 / 1386 page

Fast Ethernet Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

36-12

Freescale Semiconductor

36.9

Programming Model

The core configures an FCC to operate as an Ethernet controller using GFMR[MODE]. The receive errors

(collision, overrun, nonoctet-aligned frame, short frame, frame too long, and CRC error) are reported

through the RxBD. The transmit errors (underrun, heartbeat, late collision, retransmission limit, and carrier

sense lost) are reported through the TxBD.

The user should program the FDSR as described in Section 30.4, “FCC Data Synchronization Registers

(FDSRx),” with FDSR[SYN2] = 0xD5 and FDSR[SYN1] = 0x55.

36.10 Ethernet Command Set

The transmit and receive commands are issued to the CPCR; see Section 14.4, “Command Set.”

NOTE

Before resetting the CPM, configure TX_EN (RTS) to be an input.

Transmit commands that apply to Ethernet are described in Table 36-3.

0xE8

P128C 2

Word

(RMON mode only) The total number of packets (including bad packets) received that

were between 128 and 255 octets long inclusive (excluding framing bits but including

FCS octets).

0xEC

P256C 2

Word

(RMON mode only) The total number of packets (including bad packets) received that

were between 256 and 511 octets long inclusive (excluding framing bits but including

FCS octets).

0xF0

P512C 2

Word

(RMON mode only) The total number of packets (including bad packets) received that

were between 512 and 1023 octets long inclusive (excluding framing bits but including

FCS octets).

0xF4

P1024C 2

Word

(RMON mode only) The total number of packets (including bad packets) received that

were between 1024 and 1518 octets long inclusive (excluding framing bits but

including FCS octets).

0xF8

CAM_BUF

Word

Internal buffer for CAM result

0xFC

—

Word

Reserved, should be cleared.

0xFF

—

Byte

10 Mbps Poll Delay

100 Mbps = 0x0

10 Mbps = 0x0B (up to 100 Mhz CPM)

= 0x18 (up to 200 Mhz CPM)

= 0x32 (up to 333 Mhz CPM)

1 Offset from FCC base: 0x8400 (FCC1), 0x8500 (FCC2) and 0x8600 (FCC3); see Section 14.5.2, “Parameter RAM.”

2 32-bit (modulo 232) counters maintained by the CP; cleared by the user while the channel is disabled.

Table 36-2. Ethernet-Specific Parameter RAM (continued)

Offset1

Name

Width

Description

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