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MPC8280 bảng dữ liệu(PDF) 1191 Page - Freescale Semiconductor, Inc

tên linh kiện MPC8280
Giải thích chi tiết về linh kiện  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
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Inverse Multiplexing for ATM (IMA)
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
Freescale Semiconductor
34-45
The DCB memory area must be initialized to zero at link startup.
Figure 34-28. IMA Delay Compensation Buffer
34.4.7
IMA Exceptions
One of the four ATM interrupt queues must be dedicated to IMA events. This enables minimum latency
in dealing with the IMA state machines, and ensures that the unique format for IMA exceptions are not
confused with other exceptions. The IMA interrupt queue is defined in the IMACNTL[INTQ] parameter.
IMA events sent to this queue include only those described in this section. ICP receive events are treated
as normal receive events, and should therefore go to the interrupt queue allocated for receive events.
34.4.7.1
IMA Interrupt Queue Entry
The format for the IMA interrupt queue entries is shown in Figure 34-29
Table 34-23 describes the IMA interrupt queue entry bit fields.
0
1
23
56
78
9
10
11
12
13
14
15
OFFSET + 0
V
—
W
—
TQU TQO
—
DSL
LS
DCBO LDS GDS IFSD IFSW
OFFSET + 2 L/G
NUM
Figure 34-29. IMA Interrupt Queue Entry
IMA External Structure Region
DCB
IMAEXTBASE
DCBSP
bits 0-11
bits12-27
0000
bits 28-31
IMAEXTBASE
DCBEP
0000
IMAEXTBASE
M x 64-byte boundary
(DCBEP - DCBSP) x 16



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