MPC8280 datasheet(956/1386 Pages) FREESCALE

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Fast Communications Controllers (FCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

30-18

Freescale Semiconductor

to be a parallel I/O line, in which case the CTS signal to the FCC is always asserted. RTS is negated one

clock after the last bit in the frame.

Figure 30-9. Output Delay from RTS Asserted

If CTS is not already asserted when RTS is asserted, the delays to the first bit of data depend on when CTS

is asserted. Figure 30-10 shows that the delay between CTS and the data can be approximately 0.5 to 1 bit

times or no delay, depending on GFMR[CTSS].

Figure 30-10. Output Delay from CTS Asserted

If it is programmed to envelope the data, CTS must remain asserted during frame transmission or a CTS

lost error occurs. The negation of CTS forces RTS high and the transmit data to the idle state. If

GFMR[CTSS] = 0, the FCC must sample CTS before a CTS lost is recognized. Otherwise, the negation

of CTS immediately causes the CTS lost condition. See Figure 30-11.

1. A frame includes opening and closing flags and syncs, if present in the protocol.

TCLK

TXD

Last Bit of Frame Data

First Bit of Frame Data

Note:

(Output)

RTS

(Output)

CTS

(Input)

1. GFMR[CTSS] = 0. CTSP is a don’t care.

TCLK

TXD

Last Bit of Frame Data

First Bit Of Frame Data

Note:

CTS Sampled Low

1. GFMR[CTSS] = 1. CTSP is a don’t care.

TCLK

TXD

Last Bit of Frame Data

First Bit of Frame Data

Note:

(Output)

RTS

(Output)

CTS

(Input)

(Output)

RTS

(Output)

CTS

(Input)

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