MPC8280 datasheet(945/1386 Pages) FREESCALE

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Fast Communications Controllers (FCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

30-7

NOTE

In addition to selecting the correct mode of operation in GFMRx[MODE],

the user must issue the appropriate CP command and choose the correct

protocol in CPCR (refer to Section 14.4.1, “CP Command Register

(CPCR)”).

30.2.1

General FCC Expansion Mode Register (GFEMR)

The general FCC expansion mode register (GFEMR) defines the expansion modes. It should be

programmed according to the protocol used.

ENR

Enable receive. Enables the receiver hardware state machine for this FCC.

0 The receiver is disabled and any data in the receive FIFO buffer is lost. If ENR is cleared during

reception, the receiver aborts the current character.

1 The receiver is enabled.

ENR may be set or cleared regardless of whether serial clocks are present. Describes how to

disable and reenable an FCC. Note that the FCC provides other tools for controlling reception—the

ENTER HUNT MODE

command, CLOSE RXBD command, and RxBD[E].

ENT

Enable transmit. Enables the transmitter hardware state machine for this FCC.

0 The transmitter is disabled. If ENT is cleared during transmission, the transmitter aborts the

current character and TXD returns to idle state. Data in the transmit shift register is not sent.

1 The transmitter is enabled.

ENT can be set or cleared, regardless of whether serial clocks are present. See Section 30.12,

“Disabling the FCCs On-the-Fly,” for a description of the proper methods to disable and reenable an

FCC. Note that the FCC provides other tools for controlling transmission besides the ENT bit—the

STOP TRANSMIT

, GRACEFUL STOP TRANSMIT, and RESTART TRANSMIT commands, CTS flow control, and

TxBD[R].

28–31

MODE Channel protocol mode

0000 HDLC

0001 Reserved for RAM microcode

0010 Reserved

0011 Reserved for RAM microcode

0100 Reserved

0101 Reserved for RAM microcode

0110 Reserved

0111 Reserved for RAM microcode

1000 Reserved

1001 Reserved for RAM microcode

1010 ATM

1011 Reserved for RAM microcode

1100 Ethernet

11xx Reserved

Table 30-2. GFMR Register Field Descriptions (continued)

Bits

Name

Description

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