MPC8280 datasheet(934/1386 Pages) FREESCALE

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Multi-Channel Controllers (MCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

29-44

Freescale Semiconductor

length contains the total number of frame octets (including two or four bytes for CRC). Note that

memory allocated for buffers should be not smaller than the contents of the maximum receive

buffer length register (MRBLR). The data length does not include the time stamp.

•

Rx buffer pointer. The receive buffer pointer points to the first location of the associated data

buffer. This value must be equal to 8*n if CHAMR[TS] = 0 and equal to 8*n - 4 if CHAMR[TS]

= 1 (where n is any integer larger than 0).

29.9.2

Transmit Buffer Descriptor (TxBD)

Figure 29-22 shows the TxBD.

Table 29-22 describes TxBD fields.

234

567

Offset + 0

RT1

—

—SUD1

PAD

Offset + 2

Data Length

Offset + 4

Tx Data Buffer Pointer

Offset + 6

1 SS7 mode only. Otherwise, reserved.

Figure 29-22. MCC Transmit Buffer Descriptor (TxBD)

Table 29-22. TxBD Field Descriptions

Bits

Name

Description

Ready

0 The buffer associated with this BD is not ready for transmission. The user is free to manipulate

this BD or its associated data buffer. The CP clears this bit after the buffer has been transmitted

or after an error condition is encountered.

1 The data buffer is ready to be transmitted. The transmission may have begun, but it has not

completed. The user cannot modify this BD once this bit is set.

SS7 mode only: Retransmit.

0 Normal operation

1 The CP repeats transmission of this BD until the RT bit is cleared. After the RT bit is cleared the

CP advances to the next BD in the table. This feature is useful for automatic LSSU

retransmission.

Note: This bit is reserved in all other modes of operation.

Wrap (final BD in table)

0 This is not the last BD in the TxBD table.

1 This is the last BD in the TxBD table. After this buffer is used, the CP receives incoming data into

the first BD in the table (the BD pointed to by TBASE). The number of TxBDs in this table is

programmable and is determined the wrap bit.

Interrupt

0 No interrupt is generated after this buffer has been serviced.

1 The TXB bit in the event register is set when this buffer is serviced. TXB can cause an interrupt

if enabled.

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