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MPC8280 bảng dữ liệu(PDF) 921 Page - Freescale Semiconductor, Inc |
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MPC8280 bảng dữ liệu(HTML) 921 Page - Freescale Semiconductor, Inc |
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921 / 1386 page ![]() Multi-Channel Controllers (MCCs) MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 Freescale Semiconductor 29-31 of the managing MCC channel for that superchannel (the same MCC channel number used in the superchannel table entries corresponding to the transmit FIFOs for that superchannel). Figure 29-15. Receiver Super Channel with Slot Synchronization Example Figure 29-16 shows the SI RAM programming for the same overall configuration as the previous examples, but in this case it does not matter to the application what timeslot of a superchannel reception begins on. Thus, slot synchronization is not necessary and the timeslots do not need to be programmed as superchannelled timeslots and the CNT and BYT fields may be programed normally. 0 1 2 3–10 11–13 14 15 MCC LOOP SUPER MCSEL CNT BYT LST SI RAM Address 100 0x0 0x0 1 0 Regular Channel 101 0x1 0x01 1 First slot of the super channel 1 0 Super Channel 1 101 0x2 0x01 1 0 Super Channel 2 101 0x2 0x72 2 Regular (not first) slot of the super channel 0 0 Super Channel 2 101 0x2 0x72 0 0 Super Channel 2 100 0x5 0x0 1 0 Regular Channel 101 0x1 0x72 0 0 Super Channel 1 101 0x1 0x72 0 0 Super Channel 1 100 0x8 0x0 1 1 Regular Channel The super channel BD tables are associated with channels 1 and 2 SI RAM |
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