MPC8280 datasheet(905/1386 Pages) FREESCALE

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Multi-Channel Controllers (MCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

29-15

29.3.3.1.1

Interrupt Circular Table Entry and Interrupt Mask

(INTMSK) —AAL1 CES

Interrupt circular table entries contain information about channel-specific events. The interrupt mask

(INTMSK) provides bits for enabling/disabling the reporting of each possible event defined in the interrupt

circular table entry. Note that two CES-related interrupts provide slip indications for the MCC transmitter;

these interrupts are reflected in both the interrupt circular table entries and the INTMSK fields. They are

described in Table 29-19.

To enable an interrupt, set the corresponding bit. If a bit is cleared, no interrupt request is generated and

no new entry is written in the interrupt circular table. The user must initialize INTMSK prior to operation.

Reserved bits are cleared.

29.3.3.2

Channel Mode Register (CHAMR)—AAL1 CES

Figure 29-6 shows the user-initialized channel mode register, CHAMR, for CES operation. It is the same

as the CHAMR in transparent mode with three extra CES fields in bits 13–15.

The CHAMR in CES mode fields are described in Table 29-7.

1112131415

Interrupt Entry

—

SLIPE

SLIPS

TXB

—

NID

IDL

MRF RXF BSY RXB

INTMSK

—

CES Mask Bits

Mask Bits

—

Mask Bits

Figure 29-7. INTMSK Mask Bits

Field

MODE

POL

SYNC

—

RQN

CESM UDC UTM

Reset

—

R/W

Offset

0x1A

Figure 29-8. Channel Mode Register (CHAMR)—CES Mode

Table 29-9. CHAMR Field Descriptions—CES Mode

Bits

Name

Description

MODE

Channel mode. Selects either HDLC or transparent mode. Must be cleared for CES operation.

0 Transparent mode.

1 HDLC mode

POL

Enable polling. POL enables the transmitter to poll the TxBDs.

0 Polling is disabled (The CPM does not access the external bus to check the R bit in the TxBD).

1 Polling is enabled.

POL is used to optimize the use of the external bus. Software should always set POL at the beginning

of a transmit sequence of one or more frames. The CP clears POL when no more buffers are ready

in the transmit queue, i.e. when it finds a BD with R = 0 (for example, at the end of a frame or at the

end of a multi-frame transmission). To prevent a significant number of useless transactions on the

external bus, software should always prepare the new BD, or multiple BDs, and set BD[R] before

enabling polling.

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