MPC8280 datasheet(898/1386 Pages) FREESCALE

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Multi-Channel Controllers (MCCs)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

29-8

Freescale Semiconductor

29.3.1.2

Interrupt Mask (INTMSK)—HDLC Mode

The interrupt mask (INTMSK) provides bits for enabling/disabling the reporting of each possible event

defined in the interrupt circular table entry. For descriptions of each event bit, refer to Section 29.8.1.1,

“Interrupt Circular Table Entry.”

To enable an interrupt, set the corresponding bit. If a bit is cleared, no interrupt request is generated and

no new entry is written in the circular interrupt table. The user must initialize INTMSK prior to operation.

Reserved bits should remain cleared.

29.3.1.3

Channel Mode Register (CHAMR)—HDLC Mode

The channel mode register (CHAMR) is a user-initialized register, shown in Figure 29-4. For a

descriptions of CHAMR in transparent and SS7 modes, refer to Section 29.3.2.3 and Section 29.3.4.1

respectively. For channels that are used in conjunction with CES functionality, the user should refer to

Section 29.3.3.2, “Channel Mode Register (CHAMR)—AAL1 CES,” for additional information.

CHAMR fields are described in Table 29-4.

DTB

Data bus indicator. Selects the bus that handles transfers to and from data buffers.

0 60x bus SDMA

1 Local bus SDMA

BDB

BD bus. Selects the bus that handles transfers to/from BD and interrupt circular tables.

0 60x bus SDMA used for accessing BDs

1 Local bus SDMA used for accessing BDs

56789

Interrupt Entry

—

TXB

—

NID

IDL

MRF RXF BSY RXB

INTMSK

—

Mask Bits

—

Mask Bits

Figure 29-3. INTMSK Mask Bits

456789

Field MODE POL

IDLM

—

CRC

—

RQN

NOF

Reset

—

R/W

Offset

0x1A

Figure 29-4. Channel Mode Register (CHAMR)

Table 29-3. TSTATE High-Byte Field Descriptions (continued)

Bits

Name

Description

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