MPC8280 datasheet(824/1386 Pages) FREESCALE

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Universal Serial Bus Controller

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

27-8

Freescale Semiconductor

purposes. The USB transmitter contains four independent FIFOs, each containing 16 bytes. Endpoint 1 is

dedicated for host transactions; endpoints 2-4 are for function transactions in test mode. There is a

dedicated FIFO for each of the four supported endpoints; endpoint 1 FIFO is for host transactions. The

USB receiver has a single 16-byte FIFO.

Figure 27-4. USB Controller Block Diagram

27.5.1

USB Host Controller Transmit/Receive

The USB host controller initiates all USB transactions in the system. After the reset condition, the HOST

bit in USB mode register should be set (refer to Section 27.5.7.1, “USB Mode Register (USMOD)”) to

enable host operation. USEP1 should be programmed for host operation as described in Section 27.5.7.3,

“USB Endpoint Registers (USEP1–USEP4).”

Once enabled by setting the USMOD[EN] bit, the USB host controller waits for a packet in its transmit

FIFO. When the FIFO contains data for transmission, the host transaction begins. Figure 27-3 and

Table 27-2 describe the behavior of the USB host controller for each transaction. Low speed transactions

start with a preamble that is generated by the USB host controller state machine when the LSP bit in the

TxBD is set.

Mode register

Peripheral bus

U-bus

Command register

Port control

Transmitter

Receiver

DPLL/

Bus Interface

Rx FIFO

Tx data FIFO

mode register

Endpoint

registers

Address

Port configuration

External transceiver

16-byte

USB host

state machine

USB function

state machine

Tx data FIFO

EP0

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