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MPC8280 bảng dữ liệu(PDF) 778 Page - Freescale Semiconductor, Inc |
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MPC8280 bảng dữ liệu(HTML) 778 Page - Freescale Semiconductor, Inc |
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778 / 1386 page ![]() SCC Transparent Mode MPC8280 PowerQUICC II Family Reference Manual, Rev. 1 24-4 Freescale Semiconductor frame. Pulse operation allows an uninterrupted stream of data. However, use envelope mode to identify frames of transparent data. The sampling option determines the delay between CD and CTS being asserted and the resulting action by the SCC. Assume either that these signals are asynchronous to the data and internally synchronized by the SCC or that they are synchronous to the data with faster operation. This option allows RTS of one SCC to be connected to CD of another SCC and to have the data synchronized and bit aligned. It is also an option to link the transmitter synchronization to the receiver synchronization. Diagrams for the pulse/envelope and sampling options are shown in Section 24.4, “Achieving Synchronization in Transparent Mode.” 24.4.1.2.1 External Synchronization Example Figure 24-1 shows synchronization using external signals. Figure 24-1. Sending Transparent Frames between MPC8280s MPC8280 (A) and MPC8280 (B) exchange transparent frames and synchronize each other using RTS and CD. However, CTS is not required because transmission begins at any time. Thus, RTS is connected directly to the other MPC8280 CD pin. GSMR_H[RSYN] is not used and transmission and reception from each MPC8280 are independent. RXD CD CLK x TXD RTS CD RXD BRGO x RTS TXD CLK x BRGO x BRGO x Last Bit of Frame Data First Bit of Frame Data (Output is CLK x Input) TXD (Output is RXD Input) RTS (Output is CD Input) or CRC TxBD[L] = 1 Causes Negation of RTS CD Lost Condition Terminates Reception of Frame MPC8280 (A) MPC8280 (B) Notes: 1. Each MPC8280 generates its own transmit clocks. If the transmit and receive clocks are the same, one MPC8280 can generate transmit and receive clocks for the other MPC8280. For example, CLK x on MPC8280 (B) could be used to clock the transmitter and receiver. 2. CTS should be configured as always asserted in the parallel I/O or connected to ground externally. 3. The required GSMR configurations are DIAG= 00, CTSS=1, CTSP is a “don’t care”, CDS=1, CDP=0, TTX=1, and TRX=1. REVD and TCRC are application-dependent. 4. The transparent frame contains a CRC if TxBD[TC] is set. |
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