MPC8280 datasheet(745/1386 Pages) FREESCALE

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SCC HDLC Mode

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

22-15

Figure 22-8. SCC HDLC Interrupt Event Example

22.12 SCC HDLC Status Register (SCCS)

The SCC status register (SCCS), shown in Figure 22-9, permits monitoring of real-time status conditions

on RXD. The real-time status of CTS and CD are part of the port C parallel I/O.

4567

Field

—

Reset

0000_0000

R/W

Addr

0x11A17 (SCCS1); 0x11A37 (SCCS2); 0x11A57 (SCCS3); 0x11A77 (SCCS4)

Figure 22-9. CC HDLC Status Register (SCCS)

IDL

FLG

RXB

RXF

IDL

Line Idle

Stored in Rx Buffer

RXD

Frame

Received by HDLC

Time

Line Idle

TXD

RTS

Frame

Transmitted by HDLC

CTS

TXB

CTS

Line Idle

Stored in Tx Buffer

NOTES:

HDLC SCCE

Events

1. RXB event assumes receive buffers are 6 bytes each.

2. The second IDL event occurs after 15 ones are received in a row.

3. The FLG interrupts show the beginning and end of flag reception.

4. The FLG interrupt at the end of the frame may precede the RXF interrupt due to receive FIFO latency.

5. The CD event must be programmed in the port C parallel I/O, not in the SCC itself.

NOTES:

HDLC SCCE

Events

1. TXB event shown assumes all three bytes were put into a single buffer.

2. Example shows one additional opening flag. This is programmable.

I CR CR F

FLG

6. F = flag, A = address byte, C = control byte, I = information byte, and CR = CRC byte

C CR CR F

3. The CTS event must be programmed in the port C parallel I/O, not in the SCC itself.

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