MPC8280 datasheet(536/1386 Pages) FREESCALE

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IEEE 1149.1 Test Access Port

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

13-2

Freescale Semiconductor

Figure 13-1. Test Logic Block Diagram

The TAP consists of the signals in Table 13-1.

13.2

TAP Controller

The TAP controller is responsible for interpreting the sequence of logical values on the TMS signal. It is

a synchronous state machine that controls the operation of the JTAG logic. The value shown adjacent to

each bubble represents the value of the TMS signal sampled on the rising edge of the TCK signal.

Figure 13-2 shows the state machine.

Table 13-1. TAP Signals

Signal

Description

TCK

Test clock input to synchronize the test logic

TMS

Test mode select input (with an internal pull-up resistor) that is sampled on the rising edge of TCK to

sequence the TAP controller’s state machine

TDI

Test data input (with an internal pull-up resistor) that is sampled on the rising edge of TCK

TDO

Data output that can be three-stated and actively driven in the shift-IR and shift-DR controller states. TDO

changes on the falling edge of TCK.

TRST

Asynchronous reset with an internal pull-up resistor that provides initialization of the TAP controller and other

logic required by the standard

Boundary Scan Register

Bypass

Instruction Apply & Decode Register

8–Bit Instruction Register

TDO

TDI

TMS

TCK

TRST

TAP Controller

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